The present invention relates to an arithmetic unit which is used for quantization and inverse quantization of data.
FIG. 6 shows the basic structure of the arithmetic-logic section of a conventional signal processor using a microprogram system. In FIG. 6, the reference numeral 61 denotes an arithmetic-logic unit (ALU) and the reference numeral 62 denotes a control circuit for controlling the type of operation to be executed by the ALU 61.
The control circuit 62 controls the execution of an operation in the ALU 61 while sequentially decoding the instructions which constitute a program stored in a memory (not shown). The ALU 61 executes, on input data A and B, an operation designated by the control circuit 62, and then outputs the result of the operation as output data F. The input data A and B and the output data F are, for example, binary numbers (fixed-point numbers) in the form of two's complements.
MPEG1 is known as one of the international standards for moving picture image coding. The arithmetic-logic section shown in FIG. 6 is capable of executing quantization and inverse quantization of image data on the basis of MPEG1.
FIG. 7 is a data flow diagram illustrating an image data decoding process. In FIG. 7, the reference numeral 71 denotes a VLD section, 72 a ZZ.sup.-1 section, 73 a Q.sup.-1 section, 74 a mismatch control section, 75 an SAT (saturation) section, 76 an IDCT section, and 77 a reference memory section. The Q.sup.-1 section 73, the mismatch control section 74 and the SAT section 75 execute an inverse quantization process. The mismatch control section 74 limits the output from the Q.sup.-1 section 73 to an even or odd number in order to prevent a mismatch from arising in the IDCT section 76. Accordingly, the mismatch control section 74 executes conditional branch operations such as shown in FIGS. 8A and 8B. Quantization of image data also requires such conditional branch operations.
Operation 1 shown in FIG. 8A is a conditional branch operation to be executed depending on whether the input data B is positive, negative or zero, and also depending on whether the input data A is an even number or an odd number. Specifically, if the input data A is an odd number, the input data B is output as the output data F regardless of the value of the input data B. If the input data A is an even number, the output data F is determined depending on whether the input data B is positive, negative or zero. In other words, if the input data A is an even number and the input data B is a positive number, then 1 is added to the input data B, so that the result B+1 is output. If the input data A is an even number and the input data B is 0, then 0 (=B) is output. If the input data A is an even number and the input data B is a negative number, then 1 is subtracted from the input data B, so that the result B-1 is output.
Operation 2 shown in FIG. 8B is, as in Operation 1 described above, a conditional branch operation to be executed depending on whether the input data B is positive, negative or zero, and also depending on whether the input data A is an even number or an odd number. In Operation 2, however, the condition used in Operation 1 to obtain the output data B+1 is used as the condition for the output data B-1, while the condition used in Operation 1 to obtain the output data B-1 is used as the condition for the output data B+1.
In the case where Operation 1 shown in FIG. 8A is executed by the arithmetic-logic section of FIG. 6, the following program (procedure) is used.